The invention relates to a circuit arrangement for a video recorder, for deriving a line-frequency signal from an input signal by means of a plurality of frequency dividers, comprising:
an input terminal for receiving the input signal, and PA0 an output terminal for supplying the line-frequency signal. PA0 (a) for the VHS-NTSC standard the output of the first frequency divider is coupled to a first input of an AND-gate via the second frequency divider having a dividing ratio of 6 and to a second input of the AND gate via the third frequency divider, the output of said AND gate being coupled to the second input of the first logic circuit, PA0 (b) for the VHS-PAL standard the output of the first frequency divider is coupled, via the second frequency divider having a dividing ratio of 6, to the third frequency divider and the output of the second frequency divider is coupled via a fifth frequency divider having a dividing ratio of 2 to the second input of the first logic circuit. PA0 (c) for the Video-8 NTSC standard the output of the first frequency divider is coupled to the third frequency divider via the second frequency divider having a dividing ratio of 7, PA0 (d) for the Video-8 PAL standard the output of the first frequency divider is coupled via the second frequency divider having a dividing ratio of 7 to the third frequency divider and the output of the second frequency divider is coupled via a fifth frequency divider having a dividing ratio of 2 to the second input of the first logic circuit. PA0 (a) for the VHS NTSC standard the output of the second logic circuit is coupled to the third frequency divider having a dividing ratio of 5 via the second frequency divider having a dividing ratio of 4, PA0 (b) for the VHS PAL standard the output of the second logic circuit is coupled, by means of the second frequency divider having a dividing ratio of 3, to the second input of the first logic circuit via a fifth frequency divider having a dividing ratio of 2 and to the second input of the second logic circuit via the third frequency divider having a dividing ratio of 7 and a sixth frequency divider having a dividing ratio of 2, PA0 (c) for the Video-8-NTSC standard the output of the second logic element is coupled to the input of the second frequency divider having a dividing ratio of 4 and having its output coupled to the second input of the first logic circuit, to the second input of the second logic circuit via a fifth frequency divider having a dividing ratio of 2, and to an input of the third frequency divider having a dividing ratio of 7, PA0 (d) for the Video-8 PAL standard the output of the second logic circuit is coupled to the third frequency divider having a dividing ratio of 8 via the second frequency divider having a dividing ratio of 3, the output of said third frequency divider being coupled to the second input of the first and the second logic circuit via a sixth frequency divider having a dividing ratio of 2.
In order to reduce production costs it is desirable to equip video recorders with a single circuit board for use with different standards, for example for Video 8 or VHS in accordance with the PAL or the NTSC standard. Such a circuit board should then be provided with integrated circuits which are suitable for each of these standards and which only have to be set to the relevant standard.
A circuit arrangement of the type defined in the opening paragraph is employed in the integrated circuit TDA 3755, which serves as PAL/NTSC synchronization processor for VHS video recorders. This circuit arrangement serves to divide a signal generated by a controlled oscillator by 320 for the NTSC standard or by 321 for the PAL standard. A phase comparator generates an oscillator control signal which depends on the phase difference between a received line-frequency signal and the output signal of the circuit arrangement.
In the circuit arrangement the input signal is applied to a first input of a rejection circuit via a frefrequency divider having a dividing ratio of 2. The output of the rejection circuit is connected to a frequency divider which has a dividing ratio of 160 and which supplies the line-frequency signal. The line-frequency signal is applied to a second input of the rejection circuit via a disconnectible feedback branch comprising a further frequency divider with a dividing ratio of 2. An edge, i.e. a transition from a lower to a higher potential or, conversely, from a higher to the lower potential, in the output signal of the rejection circuit coincides with an edge in the signal on the first input if there is no edge in the signal on the second input. When an edge appears in the signal on the second input the rejection circuit ensures that the next edge of the signal on the first input produces an edge in the output signal. The feedback branch is disconnected when signals in conformity with the NTSC standard are processed.